Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops

This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed

A 90μW 12MHz Relaxation Oscillator with a -162dB FOM

A relaxation oscillator exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. A 65nm CMOS design produces a sawtooth waveform, has a frequency tuning range of 1 to 12MHz and a constant frequency-tuning gain. By minimizing and balancing noise contributions from charge and discharge mechanisms, a FOM of -162dB is achieved, which is a 7dB improvement over state-of-the-art

A 12MHz Switched-Capacitor Relaxation Oscillator with a Nearly Minimal FoM of -161dBc/Hz

In this work the phase noise performance of relaxation oscillators has been analyzed resulting in simple though precise phase noise expressions. These expressions have lead to a new relaxation oscillator topology, which exploits a noise filtering technique implemented with a switched-capacitor circuit to minimize phase noise. Measurements on a 65nm CMOS design show a sawtooth waveform, a frequency tuning range between 1 and 12MHz and a rather constant frequency tuning gain. At 12MHz oscillation frequency it consumes 90μW while the phase noise is -109dBc/Hz at 100KHz offset frequency. By minimizing and balancing noise contributions of charge and discharge mechanisms, a nearly minimal FoM of -161dBc/Hz has been achieved, which is a 6dB improvement over state-of-the-art

A high-linearity digital-to-time converter technique: constant-slope charging

A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-slope method. The proposed DTC chip realized in 65 nm CMOS consists of a voltage-controlled variable-delay element (DTC-core) driven by a 10 bit digital-to-analog converter. Measurements with a 55 MHz crystal clock demonstrate a full-scale delay programmable from 19 ps to 189 ps with a resolution from 19 fs to 185 fs. As available oscilloscopes are not good enough to reliably measure such high timing resolution, a frequency-domain method has been developed that modulates a DTC edge and derives INL from spur strength. An INL of 0.17% at 189 ps full-scale delay and 0.34% at 19 ps are measured, representing 8–9 bit effective INL-limited resolution. Output rms jitter is better than 210 fs limited by the test setup, while the DTC consumes 1.8 mW

A 1.9 μW 4.4 fJ/conversion-step, 10 bit, 1 MS/s charge redistribution ADC

A 10b SAR ADC uses a charge redistribution DAC, a two-stage comparator, and a delay-line-based controller. The ADC does not use any static bias current and power consumption is proportional to sample rate. At 1MS/s, the ADC uses 1.9μW. With 8.75 ENOB, the resulting FOM is 4.4fJ/conversion-step

A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step